1. Field of the Invention
The present invention relates to a data transfer unit and method, which permit data transfer between two systems operating on clocks asynchronous with each other.
This application claims the priority of the Japanese Patent Application No. 2002-269047 filed on Sep. 13, 2002, the entirety of which is incorporated by reference herein.
2. Description of the Related Art
For data transfer between two systems operating on clocks asynchronous with each other, one of the systems has to use the clock for the other system while the other system has to use the clock for the one system. Conventionally, this swapping between clocks is attained by accommodating a difference in timing between the clocks in an FIFO register or RAM or by generating a new clock for synchronization and transferring data synchronously with the new clock. However, the former method needs the FIFO register or RAM, which leads to an increased scale of circuit. Also, the latter method makes it necessary to input clock ratio information, timing adjusting parameter information or the like and provide a circuit which generates a clock for synchronization timing, which also leads to an increased circuit scale.
Further, the above clock swapping is attained by detecting an enable signal for data to be sent in time with a clock for a receiving end and transfer the data in time with the enable-signal detection. This method can be accomplished with an extremely small increase of the circuit scale but it is not possible unless the clock for the receiving end is sufficiently earlier than the clock for the sending end.
To solve the above problems, there has so far been proposed a system in which a data transmission permit signal and data reception permit signal are generated and the clock swapping for data transfer is done in response to the permit signals as shown in FIG. 1. The conventional clock swapping system shown in FIG. 1 will be described below.
As shown, in the conventional clock swapping system, generally indicated with a reference 100, there is provided between a data-transmission source (will be referred to as “transmitter 101” hereunder) and a data-transmission destination (will be referred to as “receiver 102” hereunder) a data transfer unit 103 which transfers data from the transmitter 101 to the receiver 102.
The transmitter 101 operates on a clock of a predetermined frequency (transmission clock ckw). The transmitter 101 outputs data on a predetermined bus width from a data output terminal thereof. For data transfer, the transmitter 101 sends transmission data dwi to the data transfer unit 103 synchronously with the transmission clock ckw.
For the data transfer, the transmitter 101 outputs also a transmission enable signal ewi indicating a transmission timing of the transmission data dwi transferred on a bus to the data transfer unit 103 synchronously with the transmission data dwi. The transmission enable signal ewi is represented by a binary signal having either of two values: H (high) and L (low) synchronous with the transmission clock ckw. The transmission enable signal ewi takes the value H when the transmission data dwi is being transferred from the transmitter 101 to the data transfer nit 103, and the value L when the transmission data dwi is not being transferred so.
The transmitter 101 receives, from the data transfer unit 103, a transmission permit signal rwo permitting to output the transmission data dwi. The transmission permit signal rwo is represented by a binary signal having either of two values: H (high) and L (low) synchronous with the transmission clock ckw. When the transmission permit signal rwo takes the value H for one clock, the transmitter 101 sends one word of the transmission data dwi to the data transfer unit 103 synchronously with the transmission clock ckw. While the transmission permit signal rwo is taking the value L, the transmitter 101 will not send the transmission data dwi and transmission enable signal ewi.
The receiver 102 operates on the transmission clock ckw and asynchronous clock (reception clock ckr). The receiver 102 is supplied at a data input terminal thereof with data on a predetermined bus width. For data transfer, the receiver 102 receives reception data dro synchronous wit a reception clock ckr from the data transfer unit 103.
The receiver 102 outputs a reception enable signal eri indicating a reception timing of the reception data dro being transferred on the bus to the data transfer unit 103 synchronously with the reception clock ckr. The reception enable signal eri is represented by a binary signal taking either of two values: H (high) and L (low) synchronous with the reception clock ckr. The reception enable signal eri takes the value H when the reception data dro is being transferred from the data transfer unit 103 to the receiver 102, and the value L when the reception data dro is not being transferred so.
The receiver 102 receives a reception permit signal rro permitting to input the reception signal dro is permitted from the data transfer unit 103. The reception permit signal rro is represented by a binary signal taking either of two values: H (high) and L (low) synchronous with the reception clock ckr. During a period for which the reception permit signal rro takes the value H, the receiver 102 can receive one word of the reception data dro from the data transfer unit 103 synchronously with the reception clock ckr. While the reception permit signal rro is taking the value L, the receiver 102 will not receive the reception data dro and send the reception enable signal eri.
When the transmission enable signal ewi takes the value H, the data transfer unit 103 receives one word of transmission data dwi and latches the data internally. Also, when the reception enable signal eri takes the value H, the receiver 102 reads one word of data latched in the data transfer unit 103.
The data transfer unit 103 is supplied with the transmission enable signal ewi from the transmitter 101, and the reception enable signal eri from the receiver 102. Also, the data transfer unit 103 outputs the transmission permit signal rwo to the transmitter 101 and the reception permit signal rro to the receiver 102.
In the above clock swapping system 100, there are cyclically done operations (S1) to (S4) as will be described below. It should be noted that when the power is supplied or when data transfer is started upon reception of an instruction for starting the data transfer, the data transfer unit 103 supplies an H-level transmission permit signal rwo to the transmitter 101 and L-level reception permit signal rro to the receiver 102.
(S1) First, upon reception of the H-level transmission permit signal rwo from the data transfer unit 102, the transmitter 101 supplies one word of the transmission data dwi to the data transfer unit 103. At this time, the transmitter 101 sets the level of the transmission enable signal ewi to H for one clock (transmission clock ckw) synchronously with the transfer of the transmission data dwi.
(S2) Next, upon reception of the H-level transmission enable signal ewi from the transmitter 101, the data transfer unit 103 supplies an H-level transmission permit signal rwo to the transmitter 101 and H-level reception permit signal rwo to the receiver 102. It should be noted that at this time, the data transfer unit 103 will take a pause of more than one period of the transmission clock ckw between a time when the transmission enable signal ewi is set to H (at the leading edge of the transmission enable signal ewi, for example) and a time when the reception permit signal rro is set to H (at the leading edge of the reception permit signal rro, for example). This is intended for assuring that storage of the transmission data dwi from the transmitter 101 into the data transfer unit 103 will positively be completed.
(S3) Upon reception of the H-level reception permit signal rro from the data transfer unit 103, the receiver 102 reads one word of the reception data dro from the data transfer unit 103. At this time, the receiver 102 sets the reception enable signal eri to H for one clock (reception clock ckr) synchronously with the transfer of the reception data dro.
(S4) Next, upon reception of the H-level reception enable signal eri from the receiver 102, the data transfer unit 103 supplies an L-level reception permit signal rro to the receiver 102 and H-level transmission permit signal rwo to the transmitter 101. It should be noted that at this time, the data transfer unit 103 will take a pause of more than one period of the reception clock ckr between a time when the reception enable signal eri is set to H (at the leading edge of the reception enable signal eri, for example) and a time when the transmission permit signal rwo is set to H (at the leading edge of the transmission permit signal rwo, for example). This is intended for assuring that reading of the reception data dro by the receiver 102 from the data transfer unit 103 will positively be completed.
The data transfer unit 103 is internally constructed as will be described below:
As shown in FIG. 1, the data transfer unit 103 includes a data latch 111 and a timing control circuit 112.
The data latch 111 operates synchronously with the transmission clock ckw and latches one word of the transmission data dwi on the bus when the transmission enable signal ewi has the value H. Also, when the reception enable signal eri is set to H, data latched in the data latch 111 is read for one word by the receiver 102.
As shown in FIG. 2, the timing control circuit 112 includes first to fourth SR flip-flop (SR-FF) circuits 121 to 124, first and second D flip-flop (D-FF) circuits 125 and 126, first and second OR circuits 127 and 128, first and second inversion circuits 129 and 130, and first and second AND circuits 131 and 132.
The first SR-FF circuit 121 is supplied at a set terminal (set) thereof with transmission enable signal ewi from the transmitter 101, and at a reset terminal (rst) with output signal from the first D-FF circuit 125. The first SR-FF circuit 121 is supplied at a clock terminal thereof with the transmission clock ckw.
The second SR-FF circuit 122 is supplied at a set terminal (set) thereof with output signal from the first D-FF circuit 125, and at a reset terminal (rst) with output signal from the third SR-FF circuit 123. The second SR-FF circuit 122 is supplied at a clock terminal thereof with the reception clock ckr.
The third SR-FF circuit 123 is supplied at a set terminal (set) thereof with the reception enable signal eri from the receiver 102, and at a reset terminal (rst) with output signal from the second D-FF circuit 126. The third SR-FF circuit 123 is supplied at a clock terminal thereof with the reception clock ckr.
The fourth SR-FF circuit 124 is supplied at a set terminal (set) thereof with output signal ewi from the second D-FF circuit 126, and at a reset terminal (rst) with output signal from the first SR-FF circuit 121. The fourth SR-FF circuit 124 is supplied at a clock terminal thereof with the transmission clock ckw.
The first D-FF circuit 125 is supplied at an input terminal (d) thereof with output signal from the first SR-FF circuit 121, and at a clock terminal with the reception clock ckr.
The second D-FF circuit 126 is supplied at an input terminal (d) thereof with output signal from the third SR-FF circuit 123, and at a clock terminal with the transmission clock ckw.
The first OR circuit 127 is supplied at one input terminal thereof with output signal from the first D-FF circuit 125, and at the other input terminal with output signal from the second SR-FF circuit 122. The second OR circuit 128 is supplied at one input terminal thereof with output signal from the second D-FF circuit 126, and at the other terminal with output signal from the fourth SR-FF circuit 124.
The first inversion circuit 129 is supplied at an input terminal thereof with output signal from the third SR-FF circuit 123, and the second inversion circuit 130 is supplied at an input terminal thereof with output signal from the first SR-FF circuit 121.
The first AND circuit 131 is supplied at one input terminal thereof with output signal from the first inversion circuit 129, and at the other input terminal with output signal from the first OR circuit 127. The second AND circuit 132 is supplied at one input terminal thereof with output signal from the second inversion circuit 130, and at the other input terminal with output signal from the second OR circuit 128.
In the timing control circuit 112 connected as above, output signal from the first AND circuit 131 is supplied as reception permit signal rro to the receiver 102, and output signal from the second AND circuit 131 is supplied as transmission permit signal rwo to the transmitter 101.
FIGS. 3 and 4 are timing diagrams of various signals when the timing control circuit constructed as above is used in the clock swapping system. FIG. 3 is a timing diagram when ckw<ckr, and FIG. 4 is a timing diagram when ckw>ckr. It should be noted that in both FIGS. 3 and 4, the reference “A” indicates output signal from the first SR-FF circuit 121, “B” indicates output signal from the first D-FF circuit 125, “C” indicates output signal from the third SR-FF circuit 123, and “D” indicates output signal from the second D-FF circuit 126.
In the conventional clock swapping system 100 which controls data transfer with the data transmission and reception permit signals as above, operations are done by repeating a sequence from issue of transmission permit signal rwo, storage of transmission data dwi, issue of reception permit signal rro to reading of reception data dro.
Therefore, the conventional clock swapping system 100 permits data transfer between two systems acting with clocks asynchronous with each other without having to use any large-capacity FIFO, RAM, etc. and whatever the ratio between the transmission and reception clocks ckw and ckr is.
The first D-FF circuit 125 is put into action at the leading edge of the reception clock ckr. However, a signal latched by the first D-FF circuit 125 is a one having been latched by the first SR-FF circuit 121 at the leading edge of the transmission clock ckw. Therefore, the time from latching of the transmission enable signal ewi by the first SR-FF circuit 121 until a next reception clock ckr rises will possibly be extremely short. In case the latching interval is so short, a so-called “metastable” phenomenon will possibly take place, resulting in an unstable operation of a downstream latch circuit (first D-FF circuit 125). Also, the second D-FF circuit 126 may possibly incur such a “metastable” phenomenon.